ECEN 350 Prelab
ECEN 350 Prelab 6 Summer 17
Question 1:
Structural programming describes the actual hardware implemented(AND and OR gates). and(x,a,b);
Behavioral programming describes the functionality of a circuit.
assign x=a&b;
Question 2:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
module halfAdder(A,B,S,C)
input A,B;
output S,C;
wire x1,x2,x3;
nand(x1,A,B);
nand(x2,A,B);
nand(x3,x1,B);
nand(S,x2,x3); nand(C,x1,x1);
endmodule
Question 3:
`timescale 1ns / 1ps `define STRLEN 15
module HalfAddTest_v;
task passTest;
input [1:0] actualOut, expectedOut;
input [ `STRLEN*8:0] testType;
inout [7:0] passed;
if(actualOut == expectedOut) begin $display ("%s passed", testType); passed = passed
+ 1 ; end
else $display ( "%s failed: %d should be %d", testType, actualOut, expectedOut);
endtask
task allPassed;
input [7:0] passed;
input [7:0] numTests;
if(passed == numTests) $display ("All tests passed"); else $display("Some tests failed");
|
endtask // Inputs | |
|
reg |
A; |
|
reg |
B; |
|
reg [7:0] // Outputs |
passed; |
|
wire |
Cout; |
|
wire |
Sum; |
// Instantiate the Device Under Test (DUT)
HalfAdd dut (
.Cout(Cout),
.Sum(Sum),
.A(A),
.B(B)
);
initial begin
// Initialize Inputs
A = 0; B = 0;
passed = 0;
// Add stimulus here
#90; A=0;B=0; #10; passTest({Cout, Sum}, 0, "0+0", passed);
#90; A=0;B=1; #10; passTest({Cout, Sum}, 1 , "0+1", passed);
#90; A=1;B=0; #10; passTest({Cout, Sum}, 1 , "1+0", passed);
#90; A=1;B=1; #10; passTest({Cout, Sum}, 2, "1+1", passed);
#90;
allPassed(passed, 4);
end
endmodule
Question 4:
sel i1 i0 | out
0 0 0 | 0
0 0 1 | 1
0 1 0 | 0
0 1 1 | 1
1 0 0 | 0
1 0 1 | 0
1 1 0 | 1 1 1 1 | 1 Question 5:
Question 6:
module two_one_mux (Y,A,B,Sel); // define the module name and its interface
output wire Y; //declare output input wire A, B, Sel; //declare inputs
wire sel_bar; //internal wires
wire w2; wire w1;
not(sel_bar,sel);//implementations of module and(w1,sel_bar,A); and(w2,Sel,B); or(Y,w1,w2);
endmodule
Question 7:
`timescale 1ns / 1ps
`define STRLEN 15
module Mux21Test_v;
task passTest; input actualOut, expectedOut; input [`STRLEN*8:0] testType;
inout [7:0] passed;
if(actualOut == expectedOut) begin $display ("%s passed", testType); passed =
passed + 1 ; end else $display ("%s failed: %d should be %d", testType, actualOut, expectedOut);
endtask
task allPassed; input [7:0] passed;
input [7:0] numTests;
if(passed == numTests) $display ( "All tests passed"); else $display("Some tests failed");
endtask
task stim;
input [1:0] newIn; input newSel; output [1:0] setIn;
output setSel;
begin #90;
setIn = newIn;
setSel = newSel;
end
endtask
// Inputs reg [1:0] in; reg sel;
reg [7:0] passed;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT) Mux21 uut (
.out(out),
.in(in),
.sel(sel)
);
initial begin
// Initialize Inputs in = 0;
sel = 0;
passed = 0;
stim(0, 0, in, sel); #10; passTest(out, 0, "Select First 0 ", passed); stim(1, 0 , in, sel); #10; passTest(out, 1, "Select First 1 ", passed); stim(2, 0, in, sel); #10; passTest(out, 0, "Select First 2", passed); stim(3, 0, in, sel); #10; passTest(out, 1, "Select First 3", passed); stim(0, 1 , in, sel); #10; passTest(out, 0, "Select Second 0 ", passed); stim(1, 1, in, sel); #10; passTest(out, 0, "Select Second 1 ", passed); stim(2, 1, in, sel); #10; passTest(out, 1 , "Select Second 2", passed); stim(3, 1, in, sel); #10; passTest(out, 1, "Select Second 3", passed);
#10;
allPassed(passed, 8);
end
endmodule
hihi
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