Engr3701 Computer Organisation And Design: Assessment Answer

If A equals B

Now arise some question how these operations are performed in ALU. These operations are performed using selection lines.

Below diagram shows selection lines for 8-bit ALU

Vhdl Design:

VHDL is a programming language. Digital system models are constructed by using this language.

Three types of models are there,

(i)Behavioral model

(ii)Dataflow model

(iii)Structural model

VHDL is an entity. This entity is help to examine the hardware modules. The entity contents are,

(i)Architecture

(ii)Package declaration

(iii)Entity declaration

(iv)Package body

(v)Configuration

Architecture:

It contains behavioral, structural, dataflow or mixed style.

Syntax:

The architecture statement is present between begin and end keywords. And the constants, variables and components are present in declarative part.

Package body:

The set of data types, functions and data types are known as package. These things are declared once we have to use any other VHDL design units.

Behavioral Modeling:

Entities are present in this modeling style. Entity means set of statements. This statements are executed sequentially. Only the statements are present process, function or procedure.

There are three types of sections are present in code.

(i)Process

(ii)Function

(iii)Procedures

These are executed sequential order. Other statements are present in outside it.

They have no limitations for sequential logic. This is the major aspect of behavioral modeling. We have to build combinational circuits and sequential circuits. IF, WAIT, CASE these are present in behavioral statements. Sequential code only used to variables. The variable values only passed out indirectly.

Dataflow Modeling:

The flow of data present in entity. This entity is described using parallel (concurrent) signals.

WHEN and GENERATE concurrent statements are comes under VHDL.

Only the operators are used to assignments. The operators are,

(i)AND

(ii)NOT

(iii)SII

(iv)*

The BLOCK is defined by special kind of assignment.

(i)The GENERATE statement

(ii)Operators

(iii)The BLOCK statements

(iv)The WHEN statements

These are used to concurrent code.

Structural Modelng:

The collection of interconnected components are known as entity. This model cannot be follow the executing order. So, these components are executed in any order. This modeling is only explains the interconnection of components. This modeling do not using any component behaviors.

The structural modeling contains, two parts. They are,

(i)Declarative part (Before the keyword begin)

(ii)Statement part (after the keyword begin)

AND GATE – logic Operation:

Figure 2 AND gate

Table 1Truth Table for AND gate

Figure 3 Waveforms for AND gate

XOR Gate –Logic operation:

Figure 4 XOR gate symbol

Table 2 Truth table for XOR gate

Figure 5 Output wave for XOR gate

Vhdl Code For A Simple Alu 

VHDL code for simple ALU is given below:

VHDL plays a vital role in electronic applications. We can design code for microcontroller, filter, ram, finite state machines, comparator, and counters and so on.

If we design 8-bit ALU in VHDL then it uses 3 bit address bus. Mostly used tool for designing ALU was VHDL Xilinx Synthesis tool ISE 13.1.

Conclusion

The simple 8-bit ALU was designed and developed by the appropriate methods and tools. For that the VHDL codding was used in this project. Here the AND gate as well as XOR gate was used to perform all kind of arithmetic as well as logical operations by the processor. And also the developed system was tested successfully. 

References

African Leadership University - Educating Africa's future leaders. (2018). Retrieved from https://www.alueducation.com/

 VHDL Primer. (2018). Retrieved from https://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html